In present computer systems memory devices for both reading and writing data, i.e. memories designated as RAM (Random Access Memory), are usually realized on the basis of memory modules of the so-called DDR type (double-data rate type). These memory modules can be accessed in read and write operations at a very high speed, thereby offering a high data bandwidth. In these memory devices, the transfer of control and data signals between memory modules of the memory device and a memory controller is synchronized on a system level to a reference clock provided by the memory controller. This means that the data transfers of all memory modules have simultaneously to be synchronized to the same clock signal. For increasing memory speeds, i.e. higher frequencies of the clock signal, and larger numbers of memory modules, the difficulties in providing the data transfer between the memory controller and the memory modules increase, and eventually a reliable data transfer becomes impossible.
In view of these problems, there has been proposed a new type of architecture for memory devices, which is of a so-called loop-forward type. This means that a plurality of memory modules is connected in series to the memory controller and that a command and address signal, a write data signal, and a read data signal are forwarded from a first memory module of the series of memory modules to the next memory module and so on. Finally, the read data signal is transferred from the last memory module of the series of memory modules to the memory controller.
The structure of a memory device corresponding to the loop-forward architecture is illustrated in FIG. 1. As can be seen, the memory device 100′ comprises a plurality of memory modules 100a′, 100b′, 100c′, and 100d′, which are identically configured. The memory device 100′ is connected to a memory controller 200′. The memory controller 200′ provides for the connection to components of a computer system, such as a central processing unit and other devices connected to a system bus (not shown).
The memory controller 200′ provides a command and address signal CA and a write data signal WD to the memory device 100′. The command and address signal CA and the write data signal WD are transmitted via a digital bus having a suitable width for carrying said signals. In the following, the command and address signal CA and the write data signal WD will be referred to in combination as command and write data signal CA, WD. Further, the memory controller 200′ provides to the memory device 100′ a clock signal CLK. The memory controller 200′ receives from the memory device 100′ a read data signal RD and a corresponding clock signal TxPCK.
Each of the memory modules 100a′, 100b′, 100c′, 100d′ comprises a memory core 110′ and a core interface 120′. Via the core interface 120′ the memory core 110′ is connected to circuitry for receiving and transmitting data.
The circuitry for receiving and transmitting data comprises for each of the memory modules 100a′, 100b′, 100c′, 100d′ a primary receiver RxP for receiving the command and write data signal CA, WD in the memory module 100a′, 100b′, 100c′, 100d′ and a primary transmitter TxP for transmitting the read data signal RD from the memory module 100a′, 100b′, 100c′, 100d′. Further, each of the memory modules 100a′, 100b′, 100c′, 100d′ comprises a secondary transmitter TxS for transmitting the command and write data signal CA, WD from the memory module 100a′, 100b′, 100c′, 100d′ and a secondary receiver RxS for receiving the read data signal RD in the memory module 100a′, 100b′, 100c′, 100d′. The primary receiver RxP, the secondary receiver RxS, the primary transmitter TxP, and the secondary transmitter TxS allow for the memory modules 100a′, 100b′, 100c′, 100d′ to be connected in series as illustrated in FIG. 1. Each of the primary and secondary receivers RxP, RxS and the primary and secondary transmitters TxP, TxS is configured to synchronize the received or transmitted signal to a respective input clock signal, thereby allowing for a transfer of the command and write data signal CA, WD and of the read data signal RD between different clock domains.
In the first memory module 100a′ the clock signal CLK provided from the memory controller is used as the input clock signal of the primary receiver RxP. The same clock signal is also used as the input clock signals of the primary transmitter TxP and the secondary transmitter TxS.
Further, the clock signal CLK provided by the memory controller is fed into a delay-locked loop (DLL) 150′. The DLL 150′ generates from its input clock signal a delayed clock signal which is used for controlling read and write operations of the memory core 110′ via the core interface 120′.
The input clock signals of the primary transmitter TxP and the secondary transmitter TxS are forwarded to a respective signal output of the first memory module 100a′ and from there to the second memory module 100b′. Further, also the input clock signal of the DLL 150′ is forwarded to a respective signal output of the first memory module 100a′ and from there to the second memory module 100b′. 
Consequently, the second memory module 100b′ receives at corresponding signal inputs the input clock signal of the DLL 150′ of the first memory module 100a′, i.e. the clock signal CLK provided by the memory controller, the input clock signal of the primary transmitter TxP of the first memory module 100a′ and the input clock signal of the secondary transmitter TxS of the first memory module 100a′. Further, the secondary memory module 100b′ receives the command and write data signal CA, WD and the read data signal RD which are transmitted from the first memory module 100a′. 
In the second memory module 100b′ it is possible to select via multiplexers 130′, 140′, which of the received clock signals are used as the input clock signals of the primary receiver RxP and the secondary receiver RxS. Generally, all these clock signals have been derived from the clock signal CLK provided by the memory controller 200′, but have been transmitted via different signal paths and therefore the signal quality may be different. In the second memory module 100b′, again the same input clock signal as for the primary receiver RxP is used as the input clock signals of the primary transmitter TxP and the secondary transmitter TxS. Like in the first memory module 100a′, the input clock signals of the primary transmitter TxP, the secondary transmitter TxS, and the DLL 150′ are forwarded to the next memory module, i.e. to the third memory module 100c′. The transfer of signals between the second memory module 100b′ and the third memory module 100c′, and also between the third memory module 100c′ and the fourth memory module 100d′ is the same as the signal transfer between the first memory module 100a′ and the second memory module 100b′. The internal signal processing in the third and fourth memory modules 100c′, 100d′ is the same as for the second memory module 100b′. From the fourth memory module 100d′, which is the last memory module of the series of memory modules, the read data signal RD is transmitted to the memory controller 200′ together with the associated input clock signal of the primary transmitter which is designated as TxPCK.
The structure of the memory modules 100a′, 100b′, 100c′, 100d′ is such that either the read data signal RD is generated in the memory module according to data stored in the memory core 110′ in response to a corresponding command received via the command and write data signal CA, WD or the read data signal RD received from another memory module located upstream in the series of memory modules is forwarded.
A major advantage of this loop-forward architecture of the memory device is that the overall latency with respect to receiving and transmitting signals is the same for each of the memory modules. For example, the first memory module 100a′ will have the shortest latency with respect to receiving the command and write data signal from the memory controller 200′, but the longest latency with respect to transmitting the read data signal RD to the memory controller 200′. Conversely, the fourth memory module 100d′ has the longest latency with respect to receiving the command and write data signal CA, WD from the memory controller 200′ and the shortest latency with respect to transmitting the read data signal RD to the memory controller 200′. Obviously, the overall latency is constant for each of the memory modules 100a′, 100b′, 100c′ and 100d′. 
However, in the memory device illustrated in FIG. 1 there exist problems with respect to the quality of the input signals received by the memory modules 100a′, 100b′, 100c′, 100d′ and by the memory controller 200′. In particular, before reaching the fourth memory module 100d′, the clock signal CLK provided by the memory controller has been passed through all the other memory modules 100a′, 100b′, and 100c′. 
Moreover, the clock signal CLK provided by the memory controller 200′ may already have undergone a substantial degradation when it is received from the memory controller 200′ in the first memory module 100a′, thereby affecting the transmission of the command and write data signal CA, WD and the read data signal RD to the next memory module and further to the other memory modules. As a result, it will generally be difficult or even impossible to receive the read data signal RD in the memory controller 200′ at a desirable speed, i.e. to use a high frequency for the clock signal CLK.